Conventionally, there has been known a technology of receiving a data signal and a clock signal and retrieving information from the data signal in accordance with timing indicated by the received clock signal. As an example of such a technology, a technology for a high-speed data receiving circuit, which retrieves information from a data bus signal (hereinafter, referred to as a DQ signal) with the rising edge and falling edge of a data strobe signal (hereinafter, referred to as a DQS signal) as a trigger, is known.
When having received a DQS signal, the high-speed data receiving circuit delays a phase of the received DQS signal by a predetermined amount from a phase of a DQ signal in order to retrieve data within a valid region (a readable range) of the DQ signal. After that, the high-speed data receiving circuit retrieves information from the DQ signal with the rising edge and falling edge of the phase-delayed DQS signal as a trigger.
Furthermore, to accurately delay the phase of the received DQS signal relative to the phase of the DQ signal, the high-speed data receiving circuit generates a clock as the basis for a phase fluctuation amount, and detects a phase shift between the generated clock and the DQS signal. Then, the high-speed data receiving circuit corrects the phase of the DQS signal on the basis of the detected phase shift and acquires information from the DQ signal.    Patent Literature 1: Japanese National Publication of International Patent Application No. 2002-531966    Patent Literature 2: Domestic Re-publication of PCT International Publication for Patent Application No. 2008-068851